Anexo 7: Instrucciones del procesador 1802

Instrucciones del microprocesador COSMAC 1802

Código Op	Mnemónica	Instrucción	Operación
0N	LDN	Load via N	M(R(N))->D; For N not 0
4N	LDA	Load Advance	M(R(N))->D; R(N)+1->R(N)
F0	LDX	Load via X	M(R(X))->D
72	LDXA	Load via X and advance	M(R(X))->D; R(X)+1->R(X)
F8	LDI	Load Immediate	M(R(P))->D; R(P)+1->R(P)
5N	STR	Store via N	D->M(R(N))
73	STXD	Store via X and Decrement	D->M(R(X)); R(X)-1->R(X)
1N	INC	Increment register N	R(N)+1->R(N)
2N	DEC	Decrement register N	R(N)-1->R(N)
60	IRX	Increment Register X	R(X)+1->R(X)
8N	GLO	Get Low register N	R(N).0->D
AN	PLO	Put Low register N	D->R(N).0
9N	GHI	Get High register N	R(N).1->D
BN	PHI	Put High register N	D->R(N).1
F1	OR	Or	M(R(X)) or D->D
F9	ORI	Or Immediate	M(R(P)) or D->D; R(P)+1->R(P)
F3	XOR	Exclusive Or	M(R(X)) xor D->D
FB	XRI	Exclusive or Immediate	M(R(P)) xor D->D; R(P)+1->R(P)
F2	AND	And	M(R(X)) and D->D
FA	ANI	And Immediate	M(R(P)) and D->D; R(P)+1->R(P)
F6	SHR	Shift Right	Shift D right; lsb(D)->DF; 0->msb(D)
76	SHRC	Shift Right with Carry	Shift D right; lsb(D)->DF; DF->msb(D)
FE	SHL	Shift Left	Shift D left; msb(D)->DF; 0->lsb(D)
7E	SHLC	Shift Left with Carry	Shift D left; msb(D)->DF; DF->lsb(D)
F4	ADD	Add	M(R(X))+D->DF,D
FC	ADI	Add Immediate	M(R(P))+D->DF,D; R(P)+1->R(P)
74	ADC	Add with Carry	M(R(X))+D+DF->DF,D
7C	ADCI	Add with Carry Immediate	M(R(P))+D+DF->DF,D; R(P)+1->R(P)
F5	SD	Subtract D	M(R(X))-D->DF,D
FD	SDI	Subtract D Immediate	M(R(P))-D->DF,D; R(P)+1->R(P)
75	SDB	Subtract D with Borrow	M(R(X))-D-DF->DF,D
7D	SDBI	Subtract D with Borrow Immediate	M(R(P))-D-DF->DF,D; R(P)+1->R(P)
F7	SM	Subtract Memory	D-M(R(X))->DF,D
FF	SMI	Subtract Memory Immediate	D-M(R(P))->DF,D; R(P)+1->R(P)
77	SMB	Subtract Memory with Borrow	D-M(R(X))-DF->DF,D;
7F	SMBI	Subtract Memory with Borrow Immediate	D-M(R(P))-DF->DF,D; R(P)+1>R(P)
30	BR	Branch	M(R(P))->R(P).0
38	NBR	No Branch	R(P)+1->R(P)
32	BZ	Branch if D=0	If D=0, M(R(P))->R(P).0 else R(P)+1->R(P)
3A	BNZ	Branch if D<>0	If D<>0, M(R(P))->R(P).0 else R(P)+1->R(P)
33	BDF	Branch if DF=1	if DF=1, M(R(P))->R(P).0 else R(P)+1->R(P)
3B	BNF	Branch if DF=0	if DF=0, M(R(P))->R(P).0 else R(P)+1->R(P)
31	BQ	Branch if Q=1	if Q=1, M(R(P))->R(P).0 else R(P)+1->R(P)
39	BNQ	Branch if Q=0	if Q=0, M(R(P))->R(P).0 else R(P)+1->R(P)
34	B1	Branch if EF1=1	if EF1=1, M(R(P))->R(P).0 else R(P)+1->R(P)
3C	BN1	Branch if EF1=0	if EF1=0, M(R(P))->R(P).0 else R(P)+1->R(P)
35	B2	Branch if EF2=1	if EF2=1, M(R(P))->R(P).0 else R(P)+1->R(P)
3D	BN2	Branch if EF2=0	if EF2=0, M(R(P))->R(P).0 else R(P)+1->R(P)
36	B3	Branch if EF3=1	if EF3=1, M(R(P))->R(P).0 else R(P)+1->R(P)
3E	BN3	Branch if EF3=0	if EF3=0, M(R(P))->R(P).0 else R(P)+1->R(P)
37	B4	Branch if EF4=1	if EF4=1, M(R(P))->R(P).0 else R(P)+1->R(P)
3F	BN4	Branch if EF4=0	if EF4=0, M(R(P))->R(P).0
C0	LBR	Long Branch	M(R(P))->R(P).1; M(R(P)+1)->R(P).0
C8	NLBR	No Long Branch	R(P)+2->R(P)
C2	LBZ	Branch if D=0	if D=0 then M(R(P))->R(P).1; M(R(P)+1)->R(P).0 else R(P)+2->R(P)
CA	LBNZ	Branch if D<>0	if D<>0 then M(R(P))->R(P).1; M(R(P)+1)->R(P).0 else R(P)+2->R(P)
C3	LBDF	Branch if DF=1	if DF=1 then M(R(P))->R(P).1; M(R(P)+1)->R(P).0 else R(P)+2->R(P)
CB	LBNF	Branch if DF=0	if DF=0 then M(R(P))->R(P).1; M(R(P)+1)->R(P).0 else R(P)+2->R(P)
C1	LBQ	Branch if Q=1	if Q=1 then M(R(P))->R(P).1; M(R(P)+1)->R(P).0 else R(P)+2->R(P)
C9	LBNQ	Branch if Q=0	if Q=0 then M(R(P))->R(P).1; M(R(P)+1)->R(P).0 else R(P)+2->R(P)
CE	LSZ	Skip if D=0	if D=0, R(P)+2->R(P) else Continue
C6	LSNZ	Skip if D<>0	if D<>0, R(P)+2->R(P) else Continue
CF	LSDF	Skip if DF=1	if DF=1, R(P)+2->R(P) else Continue
C7	LSNF	Skip if DF=0	if DF=0, R(P)+2->R(P) else Continue
CD	LSQ	Skip if Q=1	if Q=1, R(P)+2->R(P) else Continue
C5	LSNQ	Skip if Q=0	if Q=0, R(P)+2->R(P) else Continue
CC	LSIE	Skip if IE=1	if IE=0, R(P)+2->R(P) else Continue
00	IDL	Idle	Wait for DMA or Interrupt M(R(0))->Bus
C4	NOP	No operation	Continue
DN	SEP	Set P	N->P
EN	SEX	Set X	N->X
7B	SEQ	Set Q	1->Q
7A	REQ	Reset Q	0->Q
78	SAV	Save	T->M(R(X))
79	MARK	Push X,P to stack	(X,P)->T; (X,P)->M(R(2)) then P->X; R(2)-1->R(2)
70	RET	Return	M(R(X))->(X,P); R(X)+1->R(X); 1->IE
71	DIS	Disable	M(R(X))->(X,P); R(X)+1->R(X); 0->IE
61	OUT1	Output 1	M(R(X))->Bus; R(X)+1->R(X); Nlines=1
62	OUT1	Output 2	M(R(X))->Bus; R(X)+1->R(X); Nlines=2
63	OUT1	Output 3	M(R(X))->Bus; R(X)+1->R(X); Nlines=3
64	OUT1	Output 4	M(R(X))->Bus; R(X)+1->R(X); Nlines=4
65	OUT1	Output 5	M(R(X))->Bus; R(X)+1->R(X); Nlines=5
66	OUT1	Output 6	M(R(X))->Bus; R(X)+1->R(X); Nlines=6
67	OUT1	Output 7	M(R(X))->Bus; R(X)+1->R(X); Nlines=7
69	INP1	Input 1	Bus->M(R(X)); Bus->D; Nlines=1
6A	INP1	Input 2	Bus->M(R(X)); Bus->D; Nlines=2
6B	INP1	Input 3	Bus->M(R(X)); Bus->D; Nlines=3
6C	INP1	Input 4	Bus->M(R(X)); Bus->D; Nlines=4
6D	INP1	Input 5	Bus->M(R(X)); Bus->D; Nlines=5
6E	INP1	Input 6	Bus->M(R(X)); Bus->D; Nlines=6
6F	INP1	Input 7	Bus->M(R(X)); Bus->D; Nlines=7